The new & accurate techniques developed to analyze the device behaviour under various biasing and different temperature variations- Review
Abstract
This paper covers the fundamentals of SDGFETs and ADGFETs. Drain modern fashions for unmarried gate MOSFETs, SDGFETs and ADGFETs are reviewed. Within the Double gate MOS era the dominating quantum mechanical outcomes which needs to be considered in dimensional modeling are also discussed. The comparisons of drain current models for Symmetric and choppy Double gate MOSFETs are performed and proven with the effects like boundaries of the models. A quick summary of the assessment paintings is furnished. The result shows a more call for within the area of uneven Double gate modeling which may be prolonged for circuits like SRAM and RF amplifier format. The top of the line quantum mechanical results which have to be blanketed in model improvement for underneath 22nm devices are indexed.
Full Text:
PDFReferences
Thomas Skotnicki, James A.Hutchby, “The quit of CMOS scaling”, IEEE Circuits &gadgets, FEB 2005.
G. E. Moore,“ Cramming extra additives onto included circuits,” Electronics, vol. 38, pp. 114–117, 1965.
D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “tool scaling limits of Si MOSFETs and theirutility dependencies,” Proc. IEEE, vol. 89, no. three, pp. 259–288, Mar. 2001.
B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kavalieros, A. Murthy, and R. Chau “Transistor factors for 30 nmbodily gate lengths and past,” Intel Technol. J., vol. 6, no. 2, pp. 42–54, might also 2002.
[5] J. G. Fossum, V. P. Trivedi, and ok. Wu, “extraordinarily scaled absolutely depleted SOI CMOS,” in Proc. IEEE Int. SOI Conf., Oct. 2002, pp.one hundred thirty five–136.
J.-P. Colinge, “Novel gate standards for MOS devices,” Proc. 34th ESSDERC, Sep. 2004, pp. 45–49.
BSIM4.6.1 manual. (2007, can also)
T. Ytterdal, Y. Cheng and T. A. Fjeldly, “device Modeling for Analog and RF CMOS Circuit layout,” John Wiley & Sons, Ltd ISBN:0-471-49869-6, 2003.
Meyer J. E. (1971) MOS models and circuit simulation, RCA Rev., 32, forty two–sixty three.
Sodini C. G., Ko P. ok., and Moll J. L. (1984) The impact of high fields on MOS tool and circuit simulation, IEEE Trans. Electrongadgets, ED-31, 1386–1393.
H. C. Pao and C. T. Sah, “effects of diffusion currents on characteristics of steel-oxide (insulator)-semiconductor transistors,” stablestate Electron., vol. nine, no. 10, pp. 927–937, Oct. 1966.
Q. Chen, k. A. Bowman, E. M. Harrell, and J. D. Meindl, “Double jeopardy inside the nanoscale court,” IEEE Circuits gadgets magazine., vol.19, no. 1, pp. 28–34, Jan. 2003
J. P. Colinge, “multiple-gate SOI MOSFETs,” stable state Electron.,vol. 48, no. 6, pp. 897–905, Jun. 2004.
A. Ortiz-Conde and F. J. García-Sánchez, “Multi-gate three-D SOI MOSFETs because the mainstream generation in high pace CMOSapplications,” in Proc.11th IEEE Int. Symp. EDMO, Orlando, FL, Nov. 2003, pp. one hundred fifteen–121. (Invited).
Mohan V. Dunga, Chung-Hsun Lin, Xuemei (Jane) Xi, Member, Darsen D. Lu, Ali M. Niknejad,” Modeling superior FETgeneration in a Compact version,” IEEE Trans. Electron devices, 2010.
H. Lu and Y. Taur, “An analytic potential version for symmetric and asymmetric DG MOSFETs,” IEEE Trans. Electron gadgets, vol.53, no. five, pp. 1161–1168, may also 2006.
A. Ortiz-Conde, F. J. García-Sánchez, and S. Malobabic, “Analytic answer of the channel capacity in undoped symmetric dual-gateMOSFETs,” IEEE Trans. Electron gadgets, vol. fifty two, no. 7, pp. 1669–1672, Jul. 2005.
J. He, X. Xi, C. H. Lin, M. Chan, A. Niknejad, and C. Hu, “A non-fee-sheet analytic concept for undoped symmetric double-gateMOSFET from the exact solution of Poisson’s equation the use of SSP technique,” in Proc. Workshop Compact version., NSTI-Nanotech,Boston, MA, 2004, pp. 124–127.
X. Shi and M. Wong, “Analytical solutions to the one-dimensional oxidesilicon-oxide gadget,” IEEE Trans. Electron gadgets, vol. 50,no. eight, pp. 1793–1800, Aug. 2003.
J. M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, and C. Enz, “A layout oriented rate-primarily based current version forsymmetric DG MOSFET and its correlation with the EKV formalism,” stable nation Electron., vol. forty nine, no. 3, pp. 485–489, Mar. 2005.
Adelmo Ortiz-Conde, Senior Member, IEEE, Francisco J. García-Sánchez, Senior Member, IEEE, Juan Muci,SlavicaMalobabic,scholar Member, IEEE, and Juin J. Liou, Senior Member, IEEE,”A overview of center Compact fashions for Undoped Double-Gate SOIMOSFETs,” IEEE TRANSACTIONS ON ELECTRON devices, VOL. 54, NO. 1, JANUARY 2007
Jooyoung song, pupil Member, IEEE, BoYu, student Member, IEEE, Yu Yuan, and Yuan Taur, Fellow, IEEE,”A overview onCompact Modeling of more than one-Gate MOSFETs,” IEEE TRANSACTIONS ON CIRCUITS AND structures, VOL. fifty six, NO. 8,AUGUST 2009
Y. Taur, “Analytic solutions of price and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electrongadgets, vol. forty eight, no. 12, pp. 2861–2869, 2001.
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho,Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D.Kyser, “FinFETscaling to ten nm gate duration,” in IEDM Tech. Dig., 2002, pp. 251–254.
M. Anantram, M. Lundstrom, and D. Nikonov, “Modeling of nanoscale gadgets”, complaints of the IEEE, vol. 96, p.1511-1550(2008).
Refbacks
- There are currently no refbacks.