Implementation of Full Adder Using CMOS And DFAL Adiabatic Logic

Himani Sharma, Prachi Ahuja, Shylaja V karatangi, Amrita Rai, Reshu Agarwal

Abstract


Power dissipation has always been a major concern in today’s world. With increase in technology, sizing and power consumption is a great analyzing parameter. Thus, each year new technologies are designed to meet the requirements using adiabatic techniques. Adder possesses importance in designing of ALU, digital signal processing, ripple counter.  Designing of adder using conventional technique (CMOS) often create complexity and sizing issue with more energy dissipation. In this way, thus structuring adder with adiabatic system to determine previously mentioned issues. Here in this paper full adder is planned first utilizing CMOS procedure and after that utilizing DFAL (diode free adiabatic rationale) method and accordingly contrasting outcomes and ordinary cmos circuit.


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References


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