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Double Tail Dynamics Comparator with Sleep Stack Strategy

Pramila Kaniyar

Abstract


As the innovation advanced from micron to submicron the risk of spillage force dissemination emerges which rules the dissemination of element force. For recent years, innovation scaling is the most essential technique for the change of the execution of circuit regarding the force, speed and so forth. In this paper, outline and examination of twofold tail comparator with lethargic stack system is done in terms of force, defer and power delay product.Comparator is the vital circuit in the Analog to Computerized converter plan. In simple to computerized converters, the execution constraining component is the inside increase of the distinctive phases of the speakers and the comparator circuits. The exactness of the comparators which is utilized as a part of the ADC circuits is characterized as far as force and speed.A few ADCs require little defer, Low power comparators with little pass on size.So an altered configuration of twofold tail comparator is given decreased power and postpone. It is watched that in the proposed comparator force, deferral and PDP is lessened having estimations of 218.6nwatts, 276ps and 6.048 * 10-17 separately. 


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Chandrahash Patel, Dr. Veena C.S. Investigation of Comparator and their Architectures. International Journal of Multidisciplinary Consortium. 2014; 1: 1–12p.

SarangKazeminia, MortezaMousazadeh, KhayrollahHadidi and AbdollahKhoei. Rapid Low-Power Single-Stage Latched-Comparator with Improved Gain and Kickback Noise Rejection. IEEE Journal of strong state circuits. 2010; 2: 216–219p.

Swetasahu, Ajay vishwakarma. Execution of a low-kickback-commotion hooked comparator for High-speed simple to-computerized outlines in 0.18µ.International Journal of Electronics Communication and Instrumentation Engineering Research and Development. 2010; 2: 43–56p.

Raja Mohd. Noor Hafizi Raja Daud, Mamun Bin IbneReaz, and LabonnahFarzanaRahman, .Outline and Analysis of Low Power and Fast Dynamic Latch Comparator in 0.18 μm CMOS Process. International Journal of Information and Electronics Engineering. 2012; 2: 944–947p.

Boni and C.Morandi. Fast, low power BiCMOS Comparator utilizing a pMOS variable burden.IEEE Journal of strong state circuits. 1998; 33(1): 143–146p.

Anjali Sharma, Rajesh Mehra. Range and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique.Global Journal of Computer Applications. 2013; 66(4).

TanviSood, Rajesh Mehra. Outline a Low Power Half-Subtractor Using .90μm CMOS Technology. IOSR Journal of VLSI and Signal Processing. 2013; 2(3): 51–56p.

V.Kowsalya. Outline of A Low Power Double Tail Comparator Using Gated Clock and Power Gating Techniques. International Diary of Review in Electronics and Communication Engineering.2014; 2(1): 30–33p.

Wei Wang, Yu-Chi Tsao, Ken Choi, SeongMo Park, Moo-Kyoung Chung. Pipeline power lessening through single comparator-based clock gating. International System on chip Design Conference(ISOCC). 2012: 480–483p.

SamanehBabayan-Mashhadi and Reza Lotfi. Investigation and Design of a Low-Voltage Low-Power Double-Tail Comparator. IEEE Exchanges On Very Large Scale Integration (VLSI) Systems. 2014; 22(2): 343–352p.

WeixiangShen, YiciCai, Xianlong Hong, Jiang Hu. An Effective Gated Clock Tree Design Based on Activity and Register Aware Situation.IEEE Transactions on Very Large Scale Integration Systems. 200; 18(12):1639–1648p.

PradeepSingla, KamyaDhingra, Naveen Kr. Malik. DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Rationale cluster Design. International Journal of Computer Applications. 2012; 45(17): 31–36p.

B. J. Blalock. Body-driving as a Low-Voltage Analog Design Technique for CMOS innovation. in Proceedings of IEEE Southwest Symposium, Mixed Signal Design. 2000: 113–118p.

B. Goll and H. Zimmermann. A 0.12 μmCMOScomparator requiring 0.5V at 600MHz and 1.5V at 6 GHz.in Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers. 2007: 316–317p.

Nikoozadeh and B. Murmann. An examination oflatched comparator counterbalance because of burden capacitor confuse. IEEE Transactions OnCircuitsand Systems II, Express Briefs. 2006; 53(12):1398–1402p.

J. He, S. Zhan, D. Chen, and R. J. Geiger. Examinations of static and element arbitrary counterbalance voltages in element comparators. IEEE Transections on Circuits and Systems I, Regular Papers. 2009; 56(5): 911–919p.


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