Design of an Efficient Multiplier Using Transistor Level Modified Adders

Abstract

The endless improvement of modern mobile, compact devices and applications has caused an enormous effect for ultralow power circuit design. Various methods and techniques have been applied successfully to the power, performance region of the design spectrum for lower power consumption. In some applications wherever ultralow power consumption is that the primary requirement and performance is of secondary importance, a more aggressive approach is secure. The new applications mainly depend on the transistor count of circuit with longer economical battery life. The minimum energy point is obtained as an ultralow-power 0.15 V. At this minimal energy point, an ultralow-power 10T 1-bit full adder circuit at sub threshold region and it can be used for energy refrainment applications. It exhibits imperious performance in terms of design standards like average power, propagation delay and transistor count at optimal supply voltage i.e., at 0.15 V. The proposed design uses the 10T 1-bit full adder using 4-bit multiplier compared to conventional 1-bit full adder using 4-bit multiplier circuit. The performance metrics like propagation delay, average power, transistor count are reduced compared to conventional method. The designed 4-bit multiplier is simulated using Tanner tool.