Design and Implementation of Low Power Pipelined 32-bit High Performance RISC Core

Abstract

In this paper, we are proposing low power design technique in front end process. Harvard architecture is used which has distinct program memory space and data memory space. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability. To minimize the power of RISC Core, clock gating technique is used in the architectural level which is an efficient low power technique. 7-SEG LEDs are connected to the RISC IO interface for testing purpose, Verilog code is simulated using Modelsim and then implementation is done using FPGA board.