Implementation and Comparison of Floating Point Multiplier using Dadda Algorithm

Abstract

Floating point multiplication is the most useful in all the computation application like in Arithematic operation, DSP application. To achieve higher speed of the mantissa multiplication is done using Dadda multiplier which works on the bases of Dadda Algorithm. Through this architecture we gains high speed with a maximum frequency and also reduces the number of gates compared to existing multiplier and through floating point format it is possible to handle overflow or underflow conditions. This multiplier is implemented using verilog HDL and targeted for Spartan 3A and 3AN FPGA and the comparison is done with the Xilinx floating point multiplier core.