Study on a Compact and High Speed 4-bit BCD Adder

Shiby. B, Reen Paul


Speed, simplicity and efficiency in data storage are the highlights of using binary data for arithmetic operations in computer systems. But it is an irony that human beings have preferred decimal as the number base for all calculations done by hand even with the advent of binary data. Commercial databases contain more decimal data and their consequent conversion to binary and then back to decimal when used with binary arithmetic hardware reiterates the need for a decimal arithmetic hardware support in financial and commercial applications. As the use of an adder circuit is indispensable in both platforms of binary and decimal we opt the Binary Coded Decimal (BCD) adder. Compactness of gadgets, speed and abating power consumption has turned out to be an inevitable aspect over a plethora of applications. Concentrating on reducing area here we analyze different 1-bit adder cells namely SERF adder, 10T adder, 8T adder, and 6T adder cells. Simulations were done in Cadence Virtuoso tool at 180nm and 90nm for technology independence. The 6T adder outperforms in terms of area, power and PDP and is implemented in 4-bit BCD adder estimating the delay and power consumed against the conventional design in 90nm technology. Simulation results estimate that the proposed BCD adder outperforms the conventional design in all design aspects of area, power, PDP and delay.

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