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Low Power and Advanced Image Security

Satish M., Nagaraja S.C., Manoj Kumar D.K., Mukund D.S., Mrs. Nagarathna

Abstract


The main focus is to provide a low power and advanced secure compressive sensing method for image encryption and decryption. This method combines compressive sensing technique with stream cipher and block cipher to implement the secure compressive sensing. The use of stream cipher and block cipher to generate the measurement matrix. AES is one of the standard algorithm and widely used to encrypt and decrypt the data. The image encryption and decryption algorithm implemented by using AES 128-bit core. In multibit LFSR system, bits are shift in every clock cycle where single bit is shift in a conventional LFSR method. The proposed system implemented using Verilog HDL and simulated by modelsim 6.4 c and implemented in FPGA spartan 3 XC3S 200 TQ-144.

 


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References


M.P.Priyanka, E. Lakshmi prasad, Dr. A.R. Reddy. “FPGA implementation of image encryption and decryption using AES 128 bit core”.

Debarshi Datta, Bipa Datta, Himadri Sekhar Dutta. “Design and Implementation of multibit LFSR on FPGA to generate Pseudorandom sequence number”. Mar 2017.

Huang Chunguang, Cheng Hai, Song yu, Dang qun. “Permutation of image encryption system based block cipher and stream cipher algorithm”.2015.

Hrushikesh S. Deshpande, Kailash J. Karande, Altaaf O.Mulani. “Efficient implementation of AES algorithm on FPGA”. April 3-5, 2014.


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