On-Chip Structure for Timing Uncertainity Measurement Induced by Noise in Integrated Circuits

Abstract

Noise such as voltage drop and temperature in integrated circuits can cause significant performance variation and even functional failure in lower technology nodes. In this paper, we propose an on-chip structure that measures the timing uncertainty induced by noise during functional and test operations. The proposed on-chip structure facilitates the speed characterization under various workloads and test conditions. The basic structure is highly scalable and can be tailored for various applications such as silicon validation, monitoring operation condition and validating logic built-in-self-test conditions. Simulation results show that it offers very high measurement resolution in a highly efficient manner.