Improvements in the Design of Low-voltage Low-Power Double Tail Comparator

Abstract

The circuit of a standard double-tail comparator is changed for low-power and quick operation even in little provides voltages. While not complicating the planning and by adding few transistors, the feedback throughout the regeneration is reinforced, which ends up in remarkably reduced delay time. Post-layout simulation leads to a 0.18-μm CMOS technology ensure the analysis results. It is shown that within the planned dynamic comparator each the facility consumption and delay time are considerably reduced. The most clock frequency of the planned comparator may be enhanced to 2.5 and 1.1 GHz at provide voltages of 1.2 and 0.6 V, whereas, overwhelming 1.4 mW and 153 μW, severally. The quality deviation of the input-referred offset is 7.8 mV at 1.2 V supply.