Design of EDDR Architecture Based on Approximate Arithmetic Adders

Shilpa N, Shilpa K C

Abstract


This paper presents the design and simulation of design of EDDR architecture based on approximate arithmetic adders. Dynamic reconfigurable approximate arithmetic units are used to generate and get the original data. The motion estimation (ME) plays a significant role in a video coder, testing such a module is of main concern. Whereas focusing on the testing of ME in a video coding system this work presents an EDDR (error detection and data recovery) has been designed for excessive performance in software program implementation. To stumble on errors within the processing factors (PE) based totally on residue and quotient(RQ)code and for this reason, improves detection and facts recovery via the use of the proposed EDDR design for video coding testing application effectively. The design of the gadget is implemented and the language used to put in writing the code is Verilog after which is simulated using Modelsim6.4a. The software device used is Xilinx ISE design match 14.7.

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References


Advanced Video Coding for Generic Audiovisual Services, ISO/IEC 14496-10:2005 (E), Mar. 2005, ITU-T Rec.H.264(E).InformationTechnology-Coding of Audio-Visual Objects—Part 2: Visual, ISO/IEC14496-2,1999. Y. W. Huang, B. Y. Hsieh, S. Y. Chien, S. Y. Ma, and L. G. Chen, “Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 4, pp. 507–522, Apr. 2006.

M. Elgamel, A. M. Shams, and M. A. Bayoumi “A comparative analysis for low power motion estimation VLSI architectures, “Proc. IEEE Workshop Signal Process. Syst. (SiPS),Oct. 2000,pp. 149-158

I. S. Chong and A. Ortega” Dynamic voltage scaling algorithms for power constrained motion estimation,” in Proc IEEE Int. Conf. Acoust., Speech, Signal Process. (ICASSP), vol. 2 Apr. 2007,pp. II-101-II-104

D.Shin and S. K. Gupta “A re-design technique for datapath modules in error tolerant applications” D Proc. 17th Asian Test Symp. (ATS), pp. 431–437 2008

T. H. Wu, Y. L. Tsai, and S. J. Chang, “An efficient design-for-testability scheme for motion estimation in H.264/AVC,” in Proc. Int. Symp. VLSI Design, Autom. Test, Apr. 2007, pp. 1–4.

M. Y. Dong, S. H. Yang, and S. K. Lu, “Design-for-testability techniques for motion estimation computing arrays,” in Proc. Int. Conf. Commun., Circuits Syst., May 2008, pp. 1188–1191.

Y. S. Huang, C. J. Yang, and C. L. Hsu, “C-testable motion estimation design for video coding systems,” J. Electron. Sci. Technol., vol. 7, no. 4, pp. 370–374, Dec. 2009.

D. Li, M. Hu, and O. A. Mohamed, “Built-in self-test design of motion estimation computing array,” in Proc. IEEE Northeast Workshop Circuits Syst., Jun. 2004, pp. 349–352.

Y. S. Huang, C. K. Chen, and C. L. Hsu, “Efficient built-in self-test for video coding cores: A case study on motion estimation computing array,” in Proc. IEEE Asia Pacific Conf. Circuit Syst., Dec. 2008, pp. 1751–1754.

W. Y Liu, J. Y. Huang, J. H. Hong, and S. K. Lu, “Testable design and BIST techniques for systolic motion estimators in the transform domain,” in

Proc. IEEE Int. Conf. Circuits Syst., Apr. 2009, pp. 1–4.


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