Design and Analysis of 4x4 Vedic Multiplier using Carry Save and Vertical Adder

Abstract

In digital signal processing multiplication is one of the key operations between two sequences. Multiplication is used in convolution of two signals used especially for filter design operation. So it is necessary that multiplication should be performed efficiently with less area and delay. Vedic mathematics is one of the method by which we can reduced area and delay. In this paper we have design 4x4 Vedic multiplier by using the concept of Vedic mathematics; we have used Urdhva Tiryagbhyam which is one of the 16 sutras which are used in Vedic mathematics. We have design Vedic multipliers using vertical adder and carry save adder in Xilinx 14.7 software using VHDL and stimulation result are obtain and there area and delay are computed.