Implementation of Full Adder Using CMOS And DFAL Adiabatic Logic

Himani Sharma, Prachi Ahuja, Shylaja V karatangi, Amrita Rai, Reshu Agarwal


Power dissipation has always been a major concern in today’s world. With increase in technology, sizing and power consumption is a great analyzing parameter. Thus, each year new technologies are designed to meet the requirements using adiabatic techniques. Adder possesses importance in designing of ALU, digital signal processing, ripple counter.  Designing of adder using conventional technique (CMOS) often create complexity and sizing issue with more energy dissipation. In this way, thus structuring adder with adiabatic system to determine previously mentioned issues. Here in this paper full adder is planned first utilizing CMOS procedure and after that utilizing DFAL (diode free adiabatic rationale) method and accordingly contrasting outcomes and ordinary cmos circuit.

Full Text:



N.Zhuang and H. Wu, “A new design of cmos full adder”, IEEE journal of solid-state circuits”,Vol 27

G.Rama Tulasi, K. Venugopal “Design and analysis of full adder using adiabatic logic”.IJERT, Vol 1 isuue5, July 2012

P.Chandrakasan, S.Sheng, and R.W Brodersen, “Low power cmos digital design”, IEEE journal of solid state circuits, Vol 27, No.4 april1999

H.J.M Veendrick,” short circuit dissipation of static cmos circuitry and its impact on design of buffer circuits”, IEEE JSSC, August 1984

T Sakurai and A.R Newton, “Alpha power law Mosfet model and its application to cmos inverter delay and other formulas,”IEEE JSSC, Vol 25, October 1990

T Indermauer and M Horowitz, “Evaluation of charge recovery circuits and adiabatic switching for low power –––design”, Technical design IEEE symposium low power electronics, October 2002

A Kamer, J.S Denker, “2N-2D order adiabatic computation with 2N-2P and 2N-2N2P logic circuits”, In proc of the international symposium on low power design, 1995

W.C Athas, L S Vennson, J. K. Koller, “Low power digital system based on adiabatic switching principle”, IEEE Transaction on VLSI systems Vol2., 398-407

A. G Dickinson, “Adiabatic dynamic logic”,IEEE journal of solid state circuits, Vol 30

M Alioto and G Palumbo, “Performance evaluation of adiabatic gates”, IEEE trans on circuits and system, Vol27

L.A. Akers, R. Suman, “Adiabatic circuits for Low-power Logic”, IEEE papers, Aug 2002.

AtulkumarMaurya, Ganesh Kumar, “Energy Efficient Adiabatic Logic for Low-Power VLSI Application”, International Conference on Communication System and Network Technologies, 2011.

William C, Athas, Lars “J”, Svensson, JG Koller, NestorasTzartzanis& E. chou “Low Power Digital System based on Adiabatic Switching Principles”, IEEE Trans VLSI Systems, Vol 2,pp 398-407, Dec 1994.

A.P. Chandrakasn and R.W. Brodersen, Low power CMOS digital design, Klwer Academic, Norwell, Ma, 1995.

K.Nithiya, “Design of Diode-Free Adiabatic Logic Circuits Using 0.18µmUMC Technology.


  • There are currently no refbacks.