Journal of VLSI Design and Signal Processing

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Home > Archives > Vol 3, No 2,3 (2017)

Table of Contents

Articles

Impact of Doping concentration and gate voltages on Simulation of n-FinFET Aarti Bhaskar, Sanjay Mahawar, Deepak Choudhary

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A Modified Test Pattern Generation Architecture for Fault Detection in BIST M. Nandini Priya, U. Priya, D. Preethi

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Energy Efficient And High-Speed Approximate Multiplier Using Rounding Technique V. Chandran, B. Elakkiya

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Fabric Defect Identification Using Back Propagation Neural Networks Gnanaprakash V, Dr. Vanathi P.T.

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Ant Colony Optimization Based Exudates Segmentation of Fundus Images Monika Hire, Swati Shinde

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